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S25FL040A0LVFI001 参数 Datasheet PDF下载

S25FL040A0LVFI001图片预览
型号: S25FL040A0LVFI001
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位CMOS 3.0伏闪存与50MHz的SPI (串行外设接口)总线和小部门的引导和参数存储 [4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage]
分类和应用: 闪存存储
文件页数/大小: 35 页 / 1040 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.4 READ_ID Command Timing Diagram  
CS#  
SCK  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
Instruction  
24-Bit Address  
SI  
23  
21  
2
22  
3
1
0
MSB  
Manufacture Identification  
Device Identification  
High Impedance  
7
6
5
4
3
2
1
SO  
0
Table 9.2 READ_ID Data-Out Sequence  
Data  
Address  
00000h  
00001h  
Uniform  
01h  
Top Boot  
01h  
Bottom Boot  
Manufacturer Identification  
01h  
26h  
Device Identification (Memory Capacity)  
12h  
25h  
9.5  
Write Enable (WREN)  
The Write Enable (WREN) command (see Figure 9.5) sets the Write Enable Latch (WEL) bit to a 1, which  
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set  
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.  
The host system must first drive CS# low, write the WREN command, and then drive CS# high.  
Figure 9.5 Write Enable (WREN) Command Sequence  
CS#  
6
5
7
0
1
2
3
4
Mode 3  
SCK  
Mode 0  
Command  
SI  
SO  
Hi-Z  
9.6  
Write Disable (WRDI)  
The Write Disable (WRDI) command (see Figure 9.6) resets the Write Enable Latch (WEL) bit to a 0, which  
disables the device from accepting a Write Status Register, program, or erase command. The host system  
must first drive CS# low, write the WRDI command, and then drive CS# high.  
Any of following conditions resets the WEL bit:  
„ Power-up  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
17