D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
Test Condition All Speeds
1 TTL gate
3.3 V
Unit
Output Load
2.7 kΩ
Output Load Capacitance, CL
(including jig capacitance)
Device
Under
Test
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–3.0
C
L
6.2 kΩ
Input timing measurement
reference levels (See Note)
1.5
V
V
Output timing measurement
reference levels
0.5 VIO
Note: If VIO < VCC, the reference level is 0.5 VIO.
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Changing, State Unknown
Don’t Care, Any Change Permitted
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
0.5 VIO V
Input
Measurement Level
Output
0.0 V
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 13. Input Waveforms and
Measurement Levels
December 14, 2005
Am29LV640MH/L
43
SPANSION [ SPANSION ]
