D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
Min
Typ
Max
Unit
VIN = VSS to VCC
VCC = VCC max
,
ILI
Input Load Current (1)
±1.0
µA
ILIT
ILR
A9, ACC Input Load Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
VCC = VCC max; RESET# = 12.5 V
35
35
µA
µA
V
OUT = VSS to VCC
,
ILO
Output Leakage Current
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
15
15
30
20
20
50
ICC1
VCC Active Read Current (2, 3)
CE# = VIL, OE# = VIH,
mA
ICC2
ICC3
ICC4
VCC Initial Page Read Current (2, 3)
VCC Intra-Page Read Current (2, 3)
VCC Active Write Current (3, 4)
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
mA
mA
mA
10
50
20
60
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
ICC5
ICC6
ICC7
VCC Standby Current (3)
VCC Reset Current (3)
1
1
1
5
5
5
µA
µA
µA
RESET# = VSS ± 0.3 V, WP# = VIH
VIH = VCC ± 0.3 V;
Automatic Sleep Mode (3, 5)
V
IL = VSS ± 0.3 V, WP# = VIH
VIL1
VIH1
VIL2
VIH2
VHH
Input Low Voltage 1(6, 7)
–0.5
1.9
0.8
V
V
V
V
V
V
CC + 0.5
Input High Voltage 1 (6, 7)
Input Low Voltage 2 (6, 8)
0.3 x VIO
VIO + 0.5
12.5
–0.5
1.9
Input High Voltage 2 (6, 8)
Voltage for ACC Program Acceleration
VCC = 2.7 –3.6 V
VCC = 2.7 –3.6 V
11.5
Voltage for Autoselect and Temporary Sector
Unprotect
VID
11.5
12.5
V
VOL
VOH1
VOH2
VLKO
0.15 x VIO
Output Low Voltage (9)
IOL = 4.0 mA, VCC = VCC min = VIO
IOH = –2.0 mA, VCC = VCC min = VIO
IOH = –100 µA, VCC = VCC min = VIO
V
V
V
V
0.85 VIO
VIO–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (10)
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when
6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO
<
WP# = VIL is 5.0 µA.
VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH
for these connections is VIO + 0.3 V.
7. VCC voltage requirements.
8. VIO voltage requirements.
9. Includes RY/BY#
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in
progress.
10. Not 100% tested.
5. Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns.
42
Am29LV640MH/L
December 14, 2005
SPANSION [ SPANSION ]
