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AM29LV640MH112RPCI 参数 Datasheet PDF下载

AM29LV640MH112RPCI图片预览
型号: AM29LV640MH112RPCI
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(4M ×16位/ 8的M× 8位)的MirrorBit 3.0伏特,只有统一部门快闪记忆体与VersatileI / O控制 [64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control]
分类和应用: 闪存内存集成电路
文件页数/大小: 62 页 / 1108 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
Figure 22 shows the differences between DQ2 and  
grammed to “0.Only an erase operation can  
change a “0” back to a “1.Under this condition, the  
device halts the operation, and when the timing limit  
has been exceeded, DQ5 produces a “1.”  
DQ6 in graphical form.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 9 for the following discussion. When-  
ever the system initially begins reading toggle bit sta-  
tus, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically,  
the system would note and store the value of the tog-  
gle bit after the first read. After the second read, the  
system would compare the new value of the toggle bit  
with the first. If the toggle bit is not toggling, the device  
has completed the program or erase operation. The  
system can read array data on DQ7–DQ0 on the fol-  
lowing read cycle.  
In all these cases, the system must write the reset  
command to return the device to the reading the array  
(or to erase-suspend-read if the device was previously  
in the erase-suspend-program mode).  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not  
erasure has begun. (The sector erase timer does not  
apply to the chip erase command.) If additional  
sectors are selected for erasure, the entire time-out  
also applies after each additional sector erase com-  
mand. When the time-out period is complete, DQ3  
switches from a “0” to a “1.If the time between addi-  
tional sector erase commands from the system can be  
assumed to be less than 50 µs, the system need not  
monitor DQ3. See also the Sector Erase Command  
Sequence section.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of DQ5 is high  
(see the section on DQ5). If it is, the system should  
then determine again whether the toggle bit is tog-  
gling, since the toggle bit may have stopped toggling  
just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
program or erase operation. If it is still toggling, the de-  
vice did not completed the operation successfully, and  
the system must write the reset command to return to  
reading array data.  
After the sector erase command is written, the system  
should read the status of DQ7 (Data# Polling) or DQ6  
(Toggle Bit I) to ensure that the device has accepted  
the command sequence, and then read DQ3. If DQ3 is  
“1,the Embedded Erase algorithm has begun; all fur-  
ther commands (except Erase Suspend) are ignored  
until the erase operation is complete. If DQ3 is “0,the  
device will accept additional sector erase commands.  
To ensure the command has been accepted, the sys-  
tem software should check the status of DQ3 prior to  
and following each subsequent sector erase com-  
mand. If DQ3 is high on the second status check, the  
last command might not have been accepted.  
The remaining scenario is that the system initially de-  
termines that the toggle bit is toggling and DQ5 has  
not gone high. The system may continue to monitor  
the toggle bit and DQ5 through successive read cy-  
cles, determining the status as described in the previ-  
ous paragraph. Alternatively, it may choose to perform  
other system tasks. In this case, the system must start  
at the beginning of the algorithm when it returns to de-  
termine the status of the operation (top of Figure 9).  
Table 12 shows the status of DQ3 relative to the other  
status bits.  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program, erase, or  
write-to-buffer time has exceeded a specified internal  
pulse count limit. Under these conditions DQ5 pro-  
duces a “1,indicating that the program or erase cycle  
was not successfully completed.  
DQ1: Write-to-Buffer Abort  
DQ1 indicates whether a Write-to-Buffer operation  
was aborted. Under these conditions DQ1 produces a  
“1”.  
The  
system  
must  
issue  
the  
Write-to-Buffer-Abort-Reset command sequence to re-  
turn the device to reading array data. See Write Buffer  
Programming section for more details.  
The device may output a “1” on DQ5 if the system tries  
to program a “1” to a location that was previously pro-  
December 14, 2005  
Am29LV640MH/L  
39  
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