D A T A S H E E T
COMMAND DEFINITIONS
Reading Array Data in Burst Mode
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 8 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
The device powers up in the non-burst mode. To read
array data in burst mode, the system must write the
four-cycle Burst Mode Enable command sequence
(see Table 8). The device then enters burst mode. In
addition to asserting CE#, OE#, and WE# control sig-
nals, burst mode operation requires that the system
provide appropriate LBA#, BAA#, and CLK signals. For
successful burst mode reads, the following events must
occur (refer to Figures 3 and 4 for this discussion):
All addresses are latched on the falling edge of
WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever
happens first. Refer to the appropriate timing diagrams
in the AC Characteristics section.
1. The system asserts LBA# low, indicating to the de-
vice that a valid initial burst address is available on
the address bus. LBA# must be kept low until at
least the next rising edge of the CLK signal, upon
which the device loads the initial burst address.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
2. The system returns LBA# to a logic high. The device
requires that the next rising edge of CLK occur with
LBA# high for proper burst mode operation. Typi-
cally, the initial number of CLK cycles depends on
the clock frequency and the rated speed of the de-
vice.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
3. After the initial data has been read, the system as-
serts BAA# low to indicate it is ready to read the re-
maining burst read cycles. Each successive rising
edge of the CLK signal then causes the flash device
to increment the burst address and output sequen-
tial burst data.
4. When the device outputs the last word of data in the
32-word burst mode read sequence, the device out-
puts a logic low on the IND# pin. This indicates to
the system that the burst mode read sequence is
complete.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
5. To exit the burst mode, the system must write the
four-cycle Burst Mode Disable command sequence.
The device also exits the burst mode if powered
down or if RESET# is asserted. The device does not
exit the burst mode if the reset command is written.
See also “Requirements for Reading Array Data Array in
Asynchronous (Non-Burst) Mode” in the “Key to Switch-
ing Waveforms” section for more information. The Read
Operations table provides the read parameters, and
Figure 15 shows the timing diagram.
July 8, 2005
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