欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM29BL162CB70RZF 参数 Datasheet PDF下载

AM29BL162CB70RZF图片预览
型号: AM29BL162CB70RZF
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 1一M× 16位) CMOS 3.0伏只突发模式闪存 [16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 50 页 / 843 K
品牌: SPANSION [ SPANSION ]
 浏览型号AM29BL162CB70RZF的Datasheet PDF文件第12页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第13页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第14页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第15页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第17页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第18页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第19页浏览型号AM29BL162CB70RZF的Datasheet PDF文件第20页  
D A T A S H E E T  
Temporary Sector Unprotect  
HARDWARE DATA PROTECTION  
This feature allows temporary unprotection of previ-  
ously protected sectors to change data in-system. The  
Sector Unprotect mode is activated by setting the RE-  
SET# pin to VID. During this mode, formerly protected  
sectors can be programmed or erased by selecting the  
sector addresses. Once VID is removed from the RE-  
SET# pin, all the previously protected sectors are  
protected again. Figure 2 shows the algorithm, and  
Figure 23 shows the timing diagrams, for this feature.  
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection  
against inadvertent writes (refer to Table 8 for com-  
mand definitions). In addition, the following hardware  
data protection measures prevent accidental erasure  
or programming, which might otherwise be caused by  
spurious system level signals during VCC power-up and  
power-down transitions, or from system noise.  
Low VCC Write Inhibit  
When VCC is less than VLKO, the device does not ac-  
cept any write cycles. This protects data during VCC  
power-up and power-down. The command register and  
all internal program/erase circuits are disabled, and the  
device resets. Subsequent writes are ignored until VCC  
is greater than VLKO. The system must provide the  
proper signals to the control pins to prevent uninten-  
START  
RESET# = V  
(Note 1)  
ID  
tional writes when VCC is greater than VLKO  
.
Perform Erase or  
Program Operations  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE# or  
WE# do not initiate a write cycle.  
RESET# = V  
IH  
Logical Inhibit  
Write cycles are inhibited by holding any one of OE# =  
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,  
CE# and WE# must be a logical zero while OE# is a  
logical one.  
Temporary Sector  
Unprotect Completed  
(Note 2)  
Notes:  
Power-Up Write Inhibit  
1. All protected sectors unprotected.  
If WE# = CE# = VIL and OE# = VIH during power up, the  
device does not accept commands on the rising edge  
of WE#. The internal state machine is automatically  
reset to reading array data on power-up.  
2. All previously protected sectors are protected once  
again.  
Figure 2. Temporary Sector Unprotect Operation  
14  
Am29BL162C  
July 8, 2005