D A T A S H E E T
Current is reduced for the duration of the RESET# pulse.
eration is complete. If RESET# is asserted when a pro-
gram or erase operation is not executing (RY/BY# pin is
“1”), the reset operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
When RESET# is held at VSS 0.3 V, the device draws
CMOS standby current (ICC4). If RESET# is held at VIL
but not within VSS 0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the inter-
nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset op-
Table 2. Sector Address Table
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
8 Kwords
A19
0
A18
0
A17
0
A16
0
A15
0
A14
A13
0
A12
X
Address Range
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–1FFFFh
20000h–3FFFFh
40000h–5FFFFh
60000h–7FFFFh
80000h–9FFFFh
A0000h–BFFFFh
C0000h–DFFFFh
E0000h–FFFFFh
0
4 Kwords
0
0
0
0
0
0
1
0
4 Kwords
0
0
0
0
0
0
1
1
112 Kwords
128 Kwords
128 Kwords
128 Kwords
128 Kwords
128 Kwords
128 Kwords
128 Kwords
0
0
0
00100–11111
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
July 8, 2005
Am29BL162C
11
SPANSION [ SPANSION ]
