A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
4 cycles for initial access shown.
tCEZ
tCES
CE#
CLK
1
2
3
4
5
tAVC
AVD#
tAVD
tACS
tBDH
Aa
A21-A0
tBACC
tACH
Hi-Z
DQ15-DQ0
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 0.
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)
May 9, 2002
Am29BDS640G
39
SPANSION [ SPANSION ]
