A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Synchronous/Burst Read
Parameter
98
78
93
73
Description
(40 MHz) (54 MHz) (40 MHz) (54 MHz) Unit
JEDEC Standard
Latency (Even Address in Handshake
Mode)
tIACC
Max
95
87.5
95
88
ns
Parameter
98, 99
78, 79
93, 94
73, 74
Description
(40 MHz) (54 MHz) (40 MHz) (54 MHz) Unit
JEDEC Standard
Latency—(Non-Handshake or Odd
Address in Handshake mode)
tIACC
Max
Max
120
20
106
120
20
106.5
14
ns
ns
Burst Access Time Valid Clock to Output
Delay
tBACC
13.5
tACS
tACH
Address Setup Time to CLK (Note 1)
Address Hold Time from CLK (Note 1)
Data Hold Time from Next Clock Cycle
Output Enable to Output Valid
Chip Enable to High Z
Min
Min
Max
Max
Max
Max
Min
Min
Max
Min
Min
Min
Min
Min
Max
5
7
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBDH
tOE
20
13.5
13.5
20
14
tCEZ
10
10
10.5
10.5
10.5
10.5
tOEZ
Output Enable to High Z
tCES
CE# Setup Time to CLK
5
tRDYS
tRACC
tAAS
RDY Setup Time to CLK
5
4.5
20
4.5
14
Ready Access Time from CLK
Address Setup Time to AVD# (Note 1)
Address Hold Time to AVD# (Note 1)
CE# Setup Time to AVD#
AVD# Low to CLK
20
5
7
tAAH
tCAS
0
tAVC
5
tAVD
AVD# Pulse
12
70
tACC
Access Time
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
May 9, 2002
Am29BDS640G
37
SPANSION [ SPANSION ]
