A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
7 cycles for initial access shown.
tCEZ
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tACS
tBDH
A21-A0
Aa
tBACC
tACH
Hi-Z
DQ15
-DQ0
tIACC
tACC
Da
Da + 1
Da + n
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK)
38
Am29BDS640G
May 9, 2002
SPANSION [ SPANSION ]
