A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
7 cycles for initial access shown.
tCEZ
tCAS
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tAAS
tBDH
A21-A0
Aa
tBACC
tAAH
Hi-Z
DQ15
-
DQ0
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This waveform represents a synchronous burst mode, the device will also operate in handshake under a CLK synchronous
burst mode.
Figure 16. Handshake Burst Mode Read
Starting at an Even Address
42
Am29BDS640G
May 9, 2002
SPANSION [ SPANSION ]
