A D V A N C E I N F O R M A T I O N
Table 11. Burst Read Mode Settings
Address Bits
rising edges, barring any delays. The device can be set
so that the falling clock edge is active for all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
Burst Modes
A16
0
A15
RDY Configuration
Continuous
0
1
0
1
By default, the device is set so that the RDY pin will
output VOH whenever there is valid data on the outputs.
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines this setting; “1” for RDY active with data, “0” for
RDY active one clock cycle before valid data.
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
0
1
1
Note: Upon power-up or hardware reset the default setting
is continuous.
Configuration Register
Burst Active Clock Edge Configuration
Table 12 shows the address bits that determine the
configuration register settings for various device func-
tions.
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
Table 12. Burst Mode Configuration Register
Settings (Binary)
Address BIt
Function
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
A19
Set Device Read Mode
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
A18
RDY
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
A17
A16
Clock
00 = Continuous (default)
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
Burst Read Mode
A15
A14
A13
000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH
001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH
010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH
011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH
100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH
101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default)
Programmable
Wait State
A12
Note:Device will be in the default state upon power-up or hardware reset.
Note that the last two outermost boot sectors can be
locked by taking the WP# signal to VIL.
Sector Lock/Unlock Command Sequence
The sector lock/unlock command sequence allows the
system to determine which sectors are protected from
accidental writes. When the device is first powered up,
all sectors are locked. To unlock a sector, the system
must write the sector lock/unlock command sequence.
Two cycles are first written: addresses are don’t care
and data is 60h. During the third cycle, the sector
address (SLA) and unlock command (60h) is written,
while specifying with address A6 whether that sector
should be locked (A6 = VIL) or unlocked (A6 = VIH).
After the third cycle, the system can continue to lock or
unlock additional cycles, or exit the sequence by
writing F0h (reset command).
Reset Command
Writing the reset command resets the banks to the read
or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which
the system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
24
Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
