A D V A N C E I N F O R M A T I O N
Table 8. Programmable Wait State Settings
Total Initial Access
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
A14
A13
A12
Cycles
0
0
0
2
3
4
5
6
7
Standard Handshaking Operation
0
0
1
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on the clock fre-
quency.
0
1
0
0
1
1
1
0
0
Table 10 describes the typical number of clock cycles
(wait states) for various conditions with A14–A12 set to
101.
1
0
1
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
Table 10. Wait States for Standard Handshaking
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
Typical No. of Clock
Cycles after AVD# Low
3. Assumes even address.
Conditions at Address
Initial address is even
Initial address is odd
40/54 MHz
7
7
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Initial address is even,
and is at boundary crossing*
7
7
Initial address is odd,
and is at boundary crossing*
Reduced Wait-State Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
address bits A14–A12 to 010 for a clock frequency of
40 MHz or to 011 for a clock frequency of 54 MHz for
the system/device to execute at maximum speed.
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
Burst Read Mode Configuration
Table 9 describes the typical number of clock cycles
(wait states) for various conditions.
The device supports four different burst read modes:
continuous mode, and 8, 16, and 32 word linear wrap
around modes. A continuous sequence begins at the
starting address and advances the address pointer
until the burst operation is complete. If the highest
address in the device is reached during the continuous
burst read mode, the address pointer wraps around to
the lowest address.
Table 9. Initial Access Cycles vs. Frequency
System
Frequency
Range
Device
Speed
Rating
For example, an eight-word linear burst with wrap
around begins on the starting burst address written to
the device and then proceeds until the next 8 word
boundary. The address pointer then returns to the first
word of the burst sequence, wrapping back to the
starting location. The sixteen- and thirty-two linear
wrap around modes operate in a fashion similar to the
eight-word mode.
6–11 MHz
2
2
3
4
4
5
2
3
4
5
5
6
3
4
5
6
6
7
4
5
6
7
7
8
12–23 MHz
24–33 MHz
34–40 MHz
40–47 MHz
48–54 MHz
40 MHz
Table 11 shows the address bits and settings for the
four burst read modes.
54 MHz
Note: In the 8-, 16- and 32-word burst read modes, the
address pointer does not cross 64-word boundaries
(addresses which are multiples of 3Fh).
October 31, 2002
Am29BDS640G
23
SPANSION [ SPANSION ]
