A D V A N C E I N F O R M A T I O N
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 14, “Command Definitions,” on
page 29 defines the valid register command
sequences. Note that writing incorrect address and
data values or writing them in the improper sequence
rmay place the device in an unknown state. A reset
command is required to return the device to normal
operation.
555h, and address bits A19–A12 set the code to be
latched. The device will power up or after a hardware
reset with the default setting, which is in asynchronous
mode. The register must be set before the device can
enter synchronous mode. The burst mode configura-
tion register can not be changed during device opera-
tions (program, erase, or sector lock).
Refer to the AC Characteristics section for timing dia-
grams.
Power-up/
Hardware Reset
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
Asynchronous Read
Mode Only
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the
“Erase Suspend/Erase Resume Commands” section
on page 27 section for more information.
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(A19 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(A19 = 1)
Synchronous Read
Mode Only
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the “Reset
Command” section on page 24 section for more infor-
mation.
Figure 1. Synchronous/Asynchronous State
Diagram
Read Mode Setting
See also “Requirements for Asynchronous Read Oper-
ation (Non-Burst)” and “Requirements for Synchronous
(Burst) Read Operation” sections for more information.
The Asynchronous Read and Synchronous/Burst
Read tables provide the read parameters, and Figures
11, 13, and 18 show the timings.
On power-up or hardware reset, the device is set to be
in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system
operations. Address A19 determines this setting: “1’ for
asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configuration
Set Burst Mode Configuration Register
Command Sequence
The programmable wait state feature informs the
device of the number of clock cycles that must elapse
after AVD# is driven active before data will be available.
This value is determined by the input frequency of the
device. Address bits A14–A12 determine the setting
(see Table 8).
The device uses a burst mode configuration register to
set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY con-
figuration, and synchronous mode active. The burst
mode configuration register must be set before the
device will enter burst mode.
The wait state command sequence instructs the device
to set a particular number of clock cycles for the initial
access in burst mode. The number of wait states that
should be programmed into the device is directly
related to the clock frequency.
The burst mode configuration register is loaded with a
three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the
data should be C0h, address bits A11–A0 should be
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Am29BDS640G
October 31, 2002
SPANSION [ SPANSION ]
