P r e l i m i n a r y
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid
address is any sector address within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta-
neously with DQ5.
Figure 4. Data# Polling Algorithm
RDY: Ready
The RDY is a dedicated output that, by default, indicates (when at logic low) the
system should wait 1 clock cycle before expecting the next word of data. Using
the RDY Configuration Command Sequence, RDY can be set so that a logic low
indicates the system should wait 2 clock cycles before expecting valid data.
RDY functions only while reading data in burst mode. The following conditions
cause the RDY output to be low: during the initial access (in burst mode), and
after the boundary that occurs every 64 words beginning with the 64th address,
3Fh.
38
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
