P r e l i m i n a r y
Command Definitions
Table 14. Command Definitions
Bus Cycles (Notes 1–5)
Third Fourth
Command Sequence
(Notes)
First
Second
Fifth
Sixth
Addr Data Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Asynchronous Read (6)
Reset (7)
1
1
4
RA
RD
F0
XXX
555
Manufacturer ID
AA
2AA
2AA
55
55
(BA)555
(BA)555
90
90
(BA)X00
(BA)X01
0001
227E
(BA)X (Note (BA)
2200
Device ID (9)
6
555
AA
0E
9)
X0F
Sector Lock Verify (10)
Handshaking Option (11)
4
4
555
555
AA
AA
2AA
2AA
55
55
(SA)555
(BA)555
90
90
(SA)X02 0000/0001
(BA)X03 0042/0043
Program
4
3
2
2
2
2
6
6
1
1
3
555
555
XXX
XXX
XXX
BA
AA
AA
A0
80
80
90
AA
AA
B0
30
60
2AA
2AA
PA
55
55
PD
30
10
00
55
55
555
555
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program (12)
Unlock Bypass Sector Erase (12)
Unlock Bypass Chip Erase (12)
Unlock Bypass Reset (13)
Chip Erase
SA
XXX
XXX
2AA
2AA
555
555
BA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (7, 14)
Erase Resume (15)
Sector Lock/Unlock (7)
BA
BA
BA
60
55
SLA
60
C0
Set Burst Mode
Configuration Register (16)
3
1
555
55
AA
98
2AA
(CR)555
CFI Query (17)
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the rising edge of the AVD# pulse.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# pulse.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A13 uniquely select any sector.
BA = Address of the bank (A20, A19) that is being switched to
Autoselect mode, is in bypass mode, is being erased, or is being
selected for sector lock/unlock.
SLA = Address of the sector to be locked. Set sector address (SA)
and either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register address bits A19–A12.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector
11. The data is 0043h for reduced wait-state handshaking and
0042h for standard handshaking.
12. The Unlock Bypass command sequence is required prior to this
command sequence.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
13. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
5. Unless otherwise noted, address bits A20–A12 are don’t cares.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. See “Set Burst Mode Configuration Register Command
Sequence” for details.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
9. The data in the fifth cycle is 2222 for 1.8 V VIO, and 2214 for 3.0
V VIO (top boot); 2223 for 1.8 V VIO, and 2234 for 3.0 V VIO
(bottom boot).
36
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
