P r e l i m i n a r y
Standard Handshaking Operation
For optimal burst mode performance on devices without the reduced wait-state
handshaking option, the host system must set the appropriate number of wait
states in the flash device depending on the clock frequency.
Table 10 describes the typical number of clock cycles (wait states) for various
conditions with A14–A12 set to 101.
Table 10. Wait States for Standard Handshaking
Typical No. of Clock Cycles after
AVD# Low
Conditions at Address
Initial address is even
Initial address is odd
40/54 MHz
7
7
Initial address is even,
and is at boundary crossing*
7
7
Initial address is odd,
and is at boundary crossing*
* In the 8-, 16- and 32-word burst read modes, the address pointer does not cross
64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64).
Burst Read Mode Configuration
The device supports four different burst read modes: continuous mode, and 8,
16, and 32 word linear wrap around modes. A continuous sequence begins at the
starting address and advances the address pointer until the burst operation is
complete. If the highest address in the device is reached during the continuous
burst read mode, the address pointer wraps around to the lowest address.
For example, an eight-word linear burst with wrap around begins on the starting
burst address written to the device and then proceeds until the next 8 word
boundary. The address pointer then returns to the first word of the burst se-
quence, wrapping back to the starting location. The sixteen- and thirty-two linear
wrap around modes operate in a fashion similar to the eight-word mode.
Table 11 shows the address bits and settings for the four burst read modes.
Table 11. Burst Read Mode Settings
Address Bits
Burst Modes
A16
0
A15
0
Continuous
8-word linear wrap around
16-word linear wrap around
32-word linear wrap around
0
1
1
0
1
1
Note: Upon power-up or hardware reset the default setting is continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the
initial synchronous access time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set so that the falling clock
28
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
