P r e l i m i n a r y
For optimal burst mode performance on devices without the reduced wait-state
handshaking option, the host system must set the appropriate number of wait
states in the flash device depending on clock frequency and the presence of a
boundary crossing. See “Set Burst Mode Configuration Register Command Se-
quence” section on page 25 section for more information. The device will
automatically delay RDY and data by one additional clock cycle when the starting
address is odd.
The autoselect function allows the host system to determine whether the flash
device is enabled for reduced wait-state handshaking. See the “Autoselect Com-
mand Sequence” section for more information.
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while program-
ming or erasing in another bank of memory. An erase operation may also be
suspended to read from or program to another location within the same bank (ex-
cept the sector being erased). Figure 33, “Back-to-Back Read/Write Cycle
Timings,” on page 69 shows how read and write cycles may be initiated for simul-
taneous operation with zero latency. Refer to the DC Characteristics table for
read-while-program and read-while-erase current specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asynchronous or synchronous
write operation. During a synchronous write operation, to write a command or
command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to
VIH when providing an address to the device, and drive WE# and CE# to VIL, and
OE# to VIH. when writing commands or data. During an asynchronous write op-
eration, the system must drive CE#, WE#, and CLK to VIL and OE# to VIH when
providing an address, command, and data. The asynchronous and synchronous
programing operation is independent of the Set Device Read Mode bit in the Burst
Mode Configuration Register.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 8, “Programmable Wait State Settings,” on page 27 indicates the address
space that each sector occupies. The device address space is divided into four
banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain
both 8 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is
the address bits required to uniquely select a bank. Similarly, a “sector address”
is the address bits required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the active current specification for
the write mode. The AC Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. ACC
is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VID on this input, the device automatically enters the afore-
mentioned Unlock Bypass mode and uses the higher voltage on the input to
reduce the time required for program operations. The system would use a two-
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