P r e l i m i n a r y
tem must provide the proper signals to the control inputs to prevent unintentional
writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does
not accept commands on the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
V
and V Power-up And Power-down Sequencing
IO
CC
The device imposes no restrictions on VCC and VIO power-up or power-down se-
quencing. Asserting RESET# to VIL is required during the entire VCC and VIO
power sequence until the respective supplies reach their operating voltages. Once
VCC and VIO attain their respective operating voltages, de-assertion of RESET#
to VIH is permitted.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 3-6. To ter-
minate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 3-6. The system must write the reset
command to return the device to the reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the web at the following URL: http://www.amd.com/flash/cfi.
Alternatively, contact a sales office or representative for copies of these
documents.
18
Am29BDS320G
27243B1 October 1, 2003
SPANSION [ SPANSION ]
