P r e l i m i n a r y
Since the memory array is divided into four banks, each bank remains enabled
for read access until the command register contents are altered.
Address access time (tACC) is equal to the delay from stable addresses to valid
output data. The chip enable access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the outputs. The output enable access
time (tOE) is the delay from the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition.
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst
operation of a preset length. When the device first powers up, it is enabled for
asynchronous read operation.
Prior to entering burst mode, the system should determine how many wait states
are desired for the initial word (tIACC) of each burst access, what mode of burst
operation is desired, which edge of the clock will be the active clock edge, and
how the RDY signal will transition with valid data. The system would then write
the burst mode configuration register command sequence. See “Set Burst Mode
Configuration Register Command Sequence” and “Command Definitions” for fur-
ther details.
Once the system has written the “Set Burst Mode Configuration Register” com-
mand sequence, the device is enabled for synchronous reads only.
The initial word is output tIACC after the active edge of the first CLK cycle. Sub-
sequent words are output tBACC after the active edge of each successive clock
cycle, which automatically increments the internal address counter. Note that the
device has a fixed internal address boundary that occurs every 64 words, starting
at address 00003Fh. During the time the device is outputting data at this fixed
internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two
cycle latency occurs before data appears for the next address (address 000040h,
000080h, 0000C0h, etc.). The RDY output indicates this condition to the system
by pulsing low. For standard handshaking devices, there is no two cycle latency
between 3Fh and 40h (or addresses offset from 3F and 40h by a multiple of 64).
See Table 10.
For reduced wait-state handshaking devices, if the address latched is 3Dh (or off-
set from 3Dh by a multiple of 64), an additional cycle latency occurs prior to the
initial access. If the address latched is 3Eh (or offset from 3Eh by a multiple of
64) two additional cycle latency occurs prior to the initial access and the 2 cycle
latency between 3Fh and 40h (or offset from 3Fh by a multiple of 64) will not oc-
cur. For 3Fh latched addresses (or offset from 3Fh by a multiple of 64) three
additional cycle latency occurs prior to the initial access and the 2 cycle latency
between 3Fh and 40h (or offset from these addresses by a multiple of 64) will not
occur.
The device will continue to output sequential burst data, wrapping around to ad-
dress 000000h after it reaches the highest addressable memory location, until
the system drives CE# high, RESET# low, or AVD# low in conjunction with a new
address. See Table 1, “Device Bus Operations,” on page 12.
If the host system crosses the bank boundary while reading in burst mode, and
the device is not programming or erasing, a two-cycle latency will occur as de-
scribed above in the subsequent bank. If the host system crosses the bank
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