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AM29BDS320GTC9VMI 参数 Datasheet PDF下载

AM29BDS320GTC9VMI图片预览
型号: AM29BDS320GTC9VMI
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位(2M ×16位) , 1.8伏只同时读/写,突发模式闪存 [32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory]
分类和应用: 闪存
文件页数/大小: 74 页 / 1108 K
品牌: SPANSION [ SPANSION ]
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P r e l i m i n a r y  
Device Bus Operations  
This section describes the requirements and use of the device bus operations,  
which are initiated through the internal command register. The command register  
itself does not occupy any addressable memory location. The register is com-  
posed of latches that store the commands, along with the address and data  
information needed to execute the command. The contents of the register serve  
as inputs to the internal state machine. The state machine outputs dictate the  
function of the device. Table 1 lists the device bus operations, the inputs and con-  
trol levels they require, and the resulting output. The following subsections  
describe each of these operations in further detail.  
Table 1. Device Bus Operations  
CLK  
(See  
Operation  
CE#  
OE#  
WE#  
A20–0  
Addr In  
Addr In  
Addr In  
Addr In  
HIGH Z  
HIGH Z  
DQ15–0 RESET# Note) AVD#  
Asynchronous Read - Addresses Latched  
Asynchronous Read - Addresses Steady State  
Asynchronous Write  
L
L
L
L
H
H
L
I/O  
I/O  
H
H
H
H
H
L
X
X
L
L
L
L
H
H
X
X
I/O  
Synchronous Write  
L
L
I/O  
Standby (CE#)  
H
X
X
X
HIGH Z  
HIGH Z  
X
X
X
X
Hardware Reset  
Burst Read Operations  
Load Starting Burst Address  
L
L
X
L
H
H
Addr In  
HIGH Z  
X
H
H
Advance Burst to next address with  
appropriate Data presented on the Data Bus  
Burst  
Data Out  
H
Terminate current Burst read cycle  
H
X
X
X
H
H
HIGH Z  
HIGH Z  
HIGH Z  
HIGH Z  
H
L
X
X
Terminate current Burst read cycle via RESET#  
X
Terminate current Burst read cycle and start  
new Burst read cycle  
L
X
H
HIGH Z  
I/O  
H
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.  
Note: Default active edge of CLK is the rising edge.  
Enhanced VersatileIO™ (VIO) Control  
The Enhanced VersatileIO (VIO) control allows the host system to set the voltage  
levels that the device generates at its data outputs and the voltages tolerated at  
its data and address inputs to the same voltage level that is asserted on the VIO  
pin. The device is available with either 1.65–1.95 or 2.7–3.15 VIO. This allows the  
device to operate in 1.8 V or 3 V system environments as required.  
For example, a VIO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving  
and receiving signals to and from other 3 V devices on the same bus.  
Requirements for Asynchronous Read  
Operation (Non-Burst)  
To read data from the memory array, the system must first assert a valid address  
on A20–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The  
rising edge of AVD# latches the address. The data will appear on DQ15–DQ0.  
12  
Am29BDS320G  
27243B1 October 1, 2003