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AM26LV400BB-55REE 参数 Datasheet PDF下载

AM26LV400BB-55REE图片预览
型号: AM26LV400BB-55REE
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K的×8位/ 256千×16位) CMOS 3.0伏只引导扇区闪存 [4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1129 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
DQ6 also toggles during the erase-suspend-program  
RY/BY#: Ready/Busy#  
mode, and stops toggling once the Embedded Pro-  
gram algorithm is complete.  
The RY/BY# is a dedicated, open-drain output pin that  
indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after  
the rising edge of the final WE# pulse in the command  
sequence. Since RY/BY# is an open-drain output, sev-  
eral RY/BY# pins can be tied together in parallel with a  
Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-  
ure 6 shows the toggle bit algorithm. Figure 20 in the  
“AC Characteristics” section shows the toggle bit tim-  
ing diagrams. Figure 21 shows the differences be-  
tween DQ2 and DQ6 in graphical form. See also the  
subsection on DQ2: Toggle Bit II.  
pull-up resistor to VCC  
.
If the output is low (Busy), the device is actively eras-  
ing or programming. (This includes programming in  
the Erase Suspend mode.) If the output is high  
(Ready), the device is ready to read array data (includ-  
ing during the Erase Suspend mode), or is in the  
standby mode.  
DQ2: Toggle Bit II  
The “Toggle Bit II” on DQ2, when used with DQ6, indi-  
cates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit  
II is valid after the rising edge of the final WE# pulse in  
the command sequence.  
Table 6 shows the outputs for RY/BY#. Figures 14, 17  
and 18 shows RY/BY# for reset, program, and erase  
operations, respectively.  
DQ2 toggles when the system reads at addresses  
within those sectors that have been selected for era-  
sure. (The system may use either OE# or CE# to con-  
trol the read cycles.) But DQ2 cannot distinguish  
whether the sector is actively erasing or is erase-sus-  
pended. DQ6, by comparison, indicates whether the  
device is actively erasing, or is in Erase Suspend, but  
cannot distinguish which sectors are selected for era-  
sure. Thus, both status bits are required for sector and  
mode information. Refer to Table 6 to compare outputs  
for DQ2 and DQ6.  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or com-  
plete, or whether the device has entered the Erase  
Suspend mode. Toggle Bit I may be read at any ad-  
dress, and is valid after the rising edge of the final  
WE# pulse in the command sequence (prior to the  
program or erase operation), and during the sector  
erase time-out.  
During an Embedded Program or Erase algorithm op-  
eration, successive read cycles to any address cause  
DQ6 to toggle. The system may use either OE# or  
CE# to control the read cycles. When the operation is  
complete, DQ6 stops toggling.  
Figure 6 shows the toggle bit algorithm in flowchart  
form, and the section “DQ2: Toggle Bit II” explains the  
algorithm. See also the DQ6: Toggle Bit I subsection.  
Figure 20 shows the toggle bit timing diagram. Figure  
21 shows the differences between DQ2 and DQ6 in  
graphical form.  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 tog-  
gles for approximately 100 µs, then returns to reading  
array data. If not all selected sectors are protected, the  
Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are pro-  
tected.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 6 for the following discussion. When-  
ever the system initially begins reading toggle bit sta-  
tus, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically,  
the system would note and store the value of the tog-  
gle bit after the first read. After the second read, the  
system would compare the new value of the toggle bit  
with the first. If the toggle bit is not toggling, the device  
has completed the program or erase operation. The  
system can read array data on DQ7–DQ0 on the fol-  
lowing read cycle.  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is  
erase-suspended. When the device is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
DQ6 toggles. When the device enters the Erase Sus-  
pend mode, DQ6 stops toggling. However, the system  
must also use DQ2 to determine which sectors are  
erasing or erase-suspended. Alternatively, the system  
can use DQ7 (see the subsection on DQ7: Data# Poll-  
ing).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of DQ5 is high  
(see the section on DQ5). If it is, the system should  
then determine again whether the toggle bit is tog-  
gling, since the toggle bit may have stopped toggling  
just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
December 4, 2006 21523D4  
Am29LV400B  
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