CXD2510Q
2. CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(VDD = AVDD = 5.0V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Clock frequency
Clock pulse width
Setup time
Symbol Min.
Typ.
Max.
0.65
Unit
MHz
ns
fCK
t
t
t
t
t
WCK
SU
H
750
300
300
300
750
ns
Hold time
ns
Delay time
D
ns
Latch pulse width
EXCK SQCK frequency
WL
ns
fT
0.65
65
MHz
ns
EXCK SQCK pulse width tWT
750
7.5
CNIN freqency
fT
kHz
µs
CNIN pulse width
tWT
When $44 and $45 are excuted.
1/fCK
tWCK
tWCK
CLOK
DATA
XLAT
tSU
tH
tD
tWL
EXCK
CNIN
SQCK
tWT
tWT
1/fT
SBSO
SQSO
tSU
tH
Description of Functions
§1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
XLAT
D1
D2
D3
D0
D1
D2
D3
750ns or more
Data
Address
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
– 8 –
SONY [ SONY CORPORATION ]
