CXD2510Q
Pin
No.
Symbol
I/O
1, 0
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SQSO
SQCK
MUTE
SENS
XRST
DATA
XLAT
VDD
O
I
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
I
High: mute; low: release
—
I
1, Z, 0 SENS output to CPU.
System reset. Reset when low.
I
Serial data input from CPU.
I
Latch input from CPU. Serial data is latched at the falling edge.
Power supply (5V).
CLOK
SEIN
I
I
Serial data transfer clock input from CPU.
SENS input from SSP.
CNIN
DATO
XLTO
CLKO
MIRR
I
Track jump count signal input.
O
O
O
I
1, 0
1, 0
1, 0
Serial data output to SSP.
Serial data latch output to SSP. Latched at the falling edge.
Serial data transfer clock output to SSP.
Mirror signal input.
Notes)
• The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement
output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
– 5 –
SONY [ SONY CORPORATION ]
