CXD2510Q
Block Diagram
56 53
54 55
17 16
23 AVDD
FSOF
C16M
PDO
57
58
11
9
21 AVSS
33 VDD
73 VDD
12 VSS
52 VSS
Clock
generator
32K RAM
VCOI
VCOO
PCO
Digital PLL
vari-pitch
double speed
EFM
demodulator
8
Address
generator
Priority
encoder
20
FILI 19
30 PSSL
8
FILO 18
Sync
CLTV
RF
D/A
data processor
22
24
26
27
28
62
DA01 to 16
protector
16
ASYI
68
MIX
MUTE
ASYO
ASYE
WFCK
Peak detector
Digital out
Timing
generator 1
SCOR 63
EXCK 65
Subcode
P-W
60
59
DOUT
MD2
processor
SBSO
EMPH
64
61
Error corrector
Subcode
Q
processor
SQCK 67
SQSO 66
71
DATA
CPU interface
74 CLOK
MON
FSW
MDP
MDS
72
3
2
4
5
XLAT
CLV
processor
77
DATO
Servo
auto
sequencer
Timing
generator 2
79 CLKO
78 XLTO
18-times
ever sampling
filter
Noise
shaper
TEST
NC
10
4
13
70
6
50 51 32
75 69 80 76
1
25
31
Asymmetry
correction.
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
EXCK
DA10
SQSO
SQCK
MUTE
SENS
XRST
DATA
XLAT
VDD
DA11
DA12
DA13
DA14
DA15
DA16
VDD
LRCK
WDCK
PSSL
NC
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
MIRR
ASYE
ASYO
ASYI
BIAS
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15 16 17
18 19
20 21 22 24
23
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SONY [ SONY CORPORATION ]
