CXD1968AR
8. Pin Description
Pin
No.
Symbol
Type
Drive
Function
Clock and Reset
43
42
40
XTALO
XTALI
Output
Input
N/A Crystal oscillator cell output.
Crystal oscillator cell input and input for 4-20MHz tuner
clock reference.
N/A
OSCEN
Input
Input
N/A Crystal oscillator cell enable.
N/A Active low hardware reset.
6
RESETN
5V tolerant
Schmitt trigger
Dual ADC Interface
Output pin to external 0.1μF bypass capacitor for the
ADC internal DAC lower reference voltage.
55
54
61
62
DAREFM
DAREFP
REFIN
Analog output
Analog output
Analog input
N/A
Output pin to external 0.1μF bypass capacitor for the
ADC internal DAC upper reference voltage.
N/A
Reference voltage input for the I channel ADC,
normally left unconnected.
N/A
Analog input/
output
Ground reference input for REFIN (Pin 52), normally left
unconnected.
REFOUT
N/A
57
58
AINM_I
AINP_I
Analog input
Analog input
N/A Differential analog input (I channel ADC).
N/A Differential analog input (I channel ADC).
Guard ring input for I channel ADC, this should be
N/A
56
53
GUARD_I
Analog input
Analog input
connected to analog AVSS_I via a low impedance trace.
Guard ring input for Q channel ADC, this should be
N/A connected to analog AVSS_Q via a low impedance
trace.
GUARD_Q
50
49
AINM_Q
AINP_Q
Analog input
Analog input
N/A Differential analog input (Q channel ADC).
N/A Differential analog input (Q channel ADC).
MPEG2 Transport Stream Interface
22
21
20
19
18
17
14
13
TSDATA7
TSDATA6
TSDATA5
TSDATA4
TSDATA3
TSDATA2
TSDATA1
TSDATA0
Tri-state output
5V tolerant slew
rate limited[7:1]
with pull-up
MPEG2 transport stream parallel data output.
If serial mode is selected data output is either
TSDATA0 (Pin 13) or TSDATA7 (Pin 22).
Tri-state following hardware reset.
8mA
Identifies data portion of transport stream packet
(excludes parity bytes).
8mA The polarity and timing of this valid signal are
programmable.
Tri-state output
5V tolerant slew
rate limited output
with pull-up
9
TSVALID
TSCLK
Tri-state following hardware reset.
MPEG2 transport stream byte clock.
If serial MPEG2 transport stream is selected this output
12mA becomes the bit clock.
Tri-state output
5V tolerant
10
The polarity of this clock is programmable.
Tri-state following hardware reset.
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SONY [ SONY CORPORATION ]
