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CXD1199AQ 参数 Datasheet PDF下载

CXD1199AQ图片预览
型号: CXD1199AQ
PDF下载: 下载PDF文件 查看货源
内容描述: 的CD-ROM解码器 [CD-ROM DECODER]
分类和应用: 解码器消费电路商用集成电路
文件页数/大小: 42 页 / 348 K
品牌: SONY [ SONY CORPORATION ]
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CXD1199AQ  
Description of Functions  
1. Pin Description  
The pin description by function is given below.  
1-1. CD player interface (5 pins)  
This enables direct connection with the digital signal processor LSI for Sony’s CD players. Digital signal  
processor LSI for CD applications is hereafter called “CD DSP”. See 2-1-1 for the data formats.  
(1) DATA (DATA : input)  
Serial data stream from CD DSP.  
(2) BCLK (bit clock : input)  
Bit clock signal ; DATA signal strobe.  
(3) LRCK (LR clock : input)  
LR clock signal ; indicates left and right channels of DATA signals.  
(4) C2PO (C2 pointer : input)  
C2 pointer signal ; indicates that an error is contained in the DATA input.  
(5) EMP (emphasis : input)  
Emphasis positive logic signal ; indicates that emphasis has been applied to the data from CD DSP.  
1-2. Buffer memory interface (28 pins)  
This is connected to a 32 K-byte (256 K-bit) or 128 K-byte (1 M-bit) standard SRAM.  
(1) XMWR (buffer memory write : output)  
Data write strobe negative logic output signal to buffer memory.  
(2) XMOE (buffer memory output enable : output)  
Data read strobe negative logic output signal to buffer memory.  
(3) MA0 to 16 (buffer memory address : output)  
Address signals to buffer memory.  
(4) MDB0 to 7, P (buffer memory data bus : bus)  
Data bus signals of buffer memory ; pulled up by standard 25 kresistance ; MDBP pin is left open  
when connected to an 8-bit/word SRAM.  
1-3. Sub CPU interface (17 pins)  
(1) XWR (sub CPU write : input)  
Strobe negative logic input signal for writing IC internal register.  
(2) XRD (sub CPU read : input)  
Strobe negative logic input signal for reading IC internal register status.  
(3) D0 to 7 (sub CPU data bus : input/output)  
8-bit data bus.  
(4) A0 to 4 (sub CPU address : input)  
Address signal for selecting IC internal register from sub CPU.  
(5) XINT (sub CPU interrupt : output)  
Interrupt request negative logic signal to sub CPU.  
(6) XCS (chip select : input)  
IC select negative logic signal from sub CPU.  
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