CXA3106Q
CXA3106Q and Sony ADC (Demultiplex Mode) Timing
The CXA3106Q and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the A/D converters
Clock input vs. reset input
The setup time is T–1ns and the hold time is 0ns, satisfying the A/D converter specifications.
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. 1/2 clock output timing
The setup time is T–4.5ns and the hold time is T–0.5ns. (These timings also include combinations of
three A/D converters from different lots, and are defined for all operating temperatures and all operating
supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106Q vs. A/D converter 1/2 clock output
The setup time is T–3ns and the hold time is T–5ns.
CXA3106Q
T
CLK (PECL)
out
3 to 7.5ns
DSYNC (TTL)
out
0 to 1ns
1/2CLK (PECL)
out
See the CXA3026AQ/Q and
CXA3086Q specifications.
CXA3026Q
CXA3026AQ
CXA3086Q
Thold min.
T–5ns
Tsetup min. Thold min.
T–4.5ns T–0.5ns
Tsetup min.
T–3ns
4.5 to 8ns
1/2CLK (TTL)
out
DATA (TTL)
out
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SONY [ SONY CORPORATION ]
