CXA3106Q
CXA3106Q and Sony ADC (Straight Mode) Timing
The CXA3106Q and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. clock output from CXA3106Q
The setup time is T–8.5ns and the hold time is 2ns. (These timings also include combinations of three A/D
converters from different lots, and are defined for all operating temperatures and all operating supply
voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106Q vs. clock output from CXA3106Q
The setup time is T–4.5ns and the hold time is 1.5ns.
CXA3106Q
T
CLK (PECL)
out
1.5 to 4.5ns
CLK (TTL)
out
1.5 to 3ns
DSYNC (TTL)
out
Thold min.
1.5ns
Tsetup min.
T–4.5ns
CXA3026Q
CXA3026AQ
CXA3086Q
Tsetup min.
T–8.5ns
Thold min.
2ns
6.5ns min
DATA (TTL)
out
10ns max
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SONY [ SONY CORPORATION ]
