CXA3106Q
Setting Methods and Notes on Operation
Input pins
This PWB supports TTL single and PECL complementary input.
Input pins: SYNC: TTL level input, 10 to 100kHz
SYNCL: PECL low level input, 10 to 100kHz
SYNCH: PECL high level input, 10 to 100kHz
VCO:
TTL level input. This is a test pin and is therefore normally not used.
VCOL: PECL low level input. This is a test pin and is therefore normally not used.
VCOH: PECL high level input. This is a test pin and is therefore normally not used.
Output pins
This PWB supports TTL single and PECL complementary output.
DSYNCH,
DSYNCL: PECL level complementary delay SYNC outputs. The output range is 10 to 100kHz.
DSYNC:
TTL level delay SYNC output. The output range is 10 to 100kHz.
CLKH,
CLKL:
PECL level complementary CLK outputs. The output range is 10 to 120MHz.
TTL level complementary CLK outputs. The output range is 10 to 80MHz.
PECL level complementary 1/2 CLK outputs. The output range is 5 to 60MHz.
CLK,
CLKN:
CLK/2H,
CLK/2L:
CLK/2,
CLK/2N:
TTL level complementary CLK outputs. The output range is 5 to 60MHz.
Outputs the PECL amplitude threshold voltage.
VBB:
SEROUT: TTL level control register serial data output.
DIVOUT: TTL level internal programmable counter test output.
UNLOCK: TTL level UNLOCK output. This pin requires external circuits such as appropriate capacitors and
resistors.
See the IC specifications for a detailed description.
PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL
outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective
control registers. Therefore, the enable/disable settings should be made in accordance with the application.
See the following pages for the setting method.
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SONY [ SONY CORPORATION ]
