CXA2101AQ
6. Pulse interface
The sand-castle pulse is input to SCP-IN (Pin 31).
SCP is a ternary pulse which combines CBLK and CLP.
In this IC, input SCP using the pulse width shown in the figure below.
CLP and CBLK are used by each block as the clamp pulse and composite blanking pulse, respectively.
CBLK is input to the AKB timing generator, and is required to generate REF-P.
CLP
CLP ON VIH ≥ 4V
OFF VIL ≤ 3V
CBLK ON VIH ≥ 2V
OFF VIL ≤ 1V
HBLK
T1
VBLK
T2
• HBLK width:
• From VBLK end to next HBLK:T2 ≥ 9µs
T1 ≤ 25µs
The V-timing pulse is input to VTIM-IN (Pin 32).
This pulse is used as the vertical blanking pulse in the V compression mode (AKB-T (I2C bus) = 1). It is input to
the AKB timing generator, and is required to generate REF-P.
H-pulse is input to HP-IN (Pin 33).
This pulse is used as the horizontal blanking pulse in the V compression mode (AKB-T (I2C bus) = 1). It is input
to the AKB timing generator, and is required to generate REF-P.
When offset control is to be provided for the color difference input, the job of replacing the pulse with the DC
but only for a certain period is performed, and it is used in the replacement pulse generation block. Refer to
Fig. 2.
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SONY [ SONY CORPORATION ]
