CXA2101AQ
Definition of I2C BUS Registers
Slave Addresses
Slave Receiver
Slave Transmitte
84h: ADDRESS (Pin 53) = Low, 86h: ADDRESS (Pin 53) = High
85h: ADDRESS (Pin 53) = Low, 87h: ADDRESS (Pin 53) = High
Register Table
"∗": Undefined
Control Register
Sub Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
BLKSW
∗
Bit0
0
xxx00000 0h
xxx00001 1h
xxx00010 2h
xxx00011 3h
xxx00100 4h
xxx00101 5h
xxx00110 6h
xxx00111 7h
xxx01000 8h
xxx01001 9h
xxx01010 Ah
xxx01011 Bh
xxx01100 Ch
xxx01101 Dh
xxx01110 Eh
xxx01111 Fh
xxx10000 10h
xxx10001 11h
xxx10010 12h
xxx10011 13h
xxx10100 14h
xxx10101 15h
xxx10110 16h
xxx10111 17h
xxx11000 18h
PICON
RON
GON
BON
CBLKOFF AKB-T
YCbCr/MAT HYSW
INPUT-SEL
MAT-OUT
∗
PICTURE
HUE
LIMIT-LEVEL
SYSTEM
COLOR
AGING1 AGING2
YSYM1SW YM-VM
BRIGHT
SHARPNESS
R-DRIVE
G-DRIVE
B-DRIVE
R-CUTOFF
G-CUTOFF
B-CUTOFF
SUB-BRIGHT
V-TC
∗
∗
∗
∗
D-COL
CLPSW
CLP-MSK
ABL-MODE
ABL-TH
∗
∗
∗
HSEP-SEL
H-WIDTH
FIX-SYNC
CR-OFFSET 1
HD-TC HS-MASK
CB-OFFSET 1
CR OFFSET 2
SUB-CON
SUB-HUE
R-Y/R
CB OFFSET 2
SUB-COL
CTI-LEVEL
∗
∗
R-Y/B
G-Y/B
G-Y/R
LRGB2-LEVEL
PABL-LEVEL
GAMMA
BLK-BOTTOM
PRE/OVER
DC-TRAN
SUB-SHP
VM-LEV
SHP-F0
VM-DEL
LTI-LEVEL
D-PIC
Status Register
Bit7
Bit6
1
Bit5
1
Bit4
Bit3
Bit2
EH
Bit1
EV
Bit0
IK
1
1
1
– 18 –
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