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SN8F2280 参数 Datasheet PDF下载

SN8F2280图片预览
型号: SN8F2280
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 163 页 / 3660 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8F2280 Series  
USB 2.0 Full-Speed 8-Bit Micro-Controller  
the next start bit, stop bit, or not ACK bit.  
In slave mode:  
0 = Write.  
1 = Read.  
In master mode:  
0 = Transmit is not in progress.  
1 = Transmit is in progress.  
Or this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSP is in IDLE mode.  
Bit 0  
BF: Buffer Full Status bit.  
Receive:  
1 = Receive complete, MSPBUF is full.  
0 = Receive not complete, MSPBUF is empty.  
Transmit:  
1 = Data Transmit in progress (does not include the ACK and stop bits), MSPBUF is full.  
0 = Data Transmit complete (does not include the ACK and stop bits), MSPBUF is empty.  
13.3 MSP MODE REGISTER 1  
MSPM1 initial value =000000x0  
0EBH  
MSPM1  
Read/Write  
After Reset  
Bit 7  
WCOL  
R/W  
0
Bit 6  
MSPOV  
R/W  
Bit 5  
MSPENB  
R/W  
Bit 4  
CKP  
R/W  
0
Bit 3  
SLRXCKP  
R/W  
Bit 2  
MSPWK  
R/W  
Bit 1  
Bit 0  
MSPC  
R/W  
0
0
0
0
0
Bit 7  
WCOL: Write Collision Detect bit.  
Master Mode:  
0 = No collision.  
1 = A write to the MSPBUF register was attempted while the MSP conditions were not valid for a  
transmission to be started.  
Slave Mode:  
0 = No collision.  
1 = The MSPBUF register is written while it is still transmitting the previous word. (must be cleared in  
software)  
Bit 6  
MSPOV: Receive Overflow Indicator bit.  
0 = No overflow.  
1 = A byte is received while the MSPBUF register is still holding the previous byte. MSPOV is a “don’t care”  
in transmit mode. MSPOV must be cleared in software in either mode. (must be cleared in software)  
Bit 5  
Bit 4  
MSPENB: Main Serial Port Communication Enable.  
0 = Disables Main Serial Port and configures these pins as I/O port pins.  
1 = Enables Main Serial Port and configures SCL and SDA as the source of the serial port pins.  
CKP: SCL Clock Priority Control bit.  
In MSP Slave mode:  
0 = Hold SCL keeping Low. (Ensure data setup time and Slave device ready)  
1 = Release SCL Clock.  
(Slave Transistor mode CKP function always enables, Slave Receiver CKP function control by SLRXCKP)  
In MSP Master mode:  
Unused.  
Bit 3  
SLRXCKP: Slave Receiver mode SCL Clock Priority Control bit.  
In MSP Slave Receiver mode:  
SONiX TECHNOLOGY CO., LTD  
Page 135  
Version 1.1  
 
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