SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
13.6 Slave Mode Operation
When an address is matched or data transfer after and address match is received, the hardware automatically will
generate the acknowledge (ACK_) signal, and load MSPBUF (MSP buffer register) with the received data from
MSPSR.
There are some conditions that will cause MSP function will not reply ACK_ signal:
z
z
Data Buffer already full: BF=1 (MSPSTAT bit 0), when another transfer was received.
Data Overflow: MSPOV=1 (MSPM1 bit 6), when another transfer was received.
When BF=1, means MSPBUF data is still not read by MCU, so MSPSR will not load data into MSPBUF, but MSPIRQ
and MSPOV bit will still set to 1. BF bit will be clear automatically when reading MSPBUF register. MSPOV bit must be
clear through by Software.
13.6.1 Addressing
When MSP Slave function has been enabled, it will wait a START signal occur. Following the START signal, 8-bit
address will shift into the MSPSR register. The data of MSPSR[7:1] is compare with MSPADR register on the falling
edge of eight SCL pulse, If the address are the same, the BF and MSPOV bit are both clear, the following event occur:
1. MSPSR register is loaded into MSPBUF on the falling edge of eight SCL pulse.
2. Buffer full bit (BF) is set to 1, on the falling edge of eight SCL pulse.
3. An ACK_ signal is generated.
4. MSP interrupt request MSPIRQ is set on the falling edge of ninth SCL pulse.
Status when Data is
Received
MSPSPÆ MSPBUF
Reply an ACK_ signal
Set MSPIRQ
BF
0
MSPOV
0
*1
0
Yes
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
*0
1
1
1
No
Data Received Action Table
Note: BF=0, MSPOV=1 shows the software is not set properly to clear Overflow register.
13.6.2 Slave Receiving
When the R/W bit of address byte =0 and address is matched, the R/W bit of MSPSTAT is cleared. The address will be
load into MSPBUF. After reply an ACK_ signal, MSP will receive data every 8 clock. The CKP function enable or
disable (Default) is controlled by SLRXCKP bit and data latch edge -Rising edge (Default) or Falling edge is controlled
by CKE bit.
When overflow occur, no acknowledge signal replied which either BF=1 or MSPOV=1.
MSP interrupt is generated in every data transfer. The MSPIRQ bit must be clear by software.
Following is the Slave Receiving Diagram:
SLRXCKP=0
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