欢迎访问ic37.com |
会员登录 免费注册
发布采购

SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号SP37E760的Datasheet PDF文件第31页浏览型号SP37E760的Datasheet PDF文件第32页浏览型号SP37E760的Datasheet PDF文件第33页浏览型号SP37E760的Datasheet PDF文件第34页浏览型号SP37E760的Datasheet PDF文件第36页浏览型号SP37E760的Datasheet PDF文件第37页浏览型号SP37E760的Datasheet PDF文件第38页浏览型号SP37E760的Datasheet PDF文件第39页  
5.4.4 REGISTER DEFINITIONS  
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are  
supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict  
with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that  
mode. The port registers vary depending on the mode field in the ecr (Table 19). Table 18 lists these dependencies.  
Operation of the devices in modes other that those specified is undefined.  
Table 18 - ECP Register Definitions  
NAME  
ADDRESS (Note 1)  
+000h R/W  
+000h R/W  
+001h R/W  
+002h R/W  
+400h R/W  
+400h R/W  
+400h R/W  
+400h R  
ECP MODES  
FUNCTION  
Data Register  
ECP FIFO (Address)  
Status Register  
data  
000-001  
011  
All  
ecpAFifo  
dsr  
dcr  
All  
Control Register  
cFifo  
ecpDFifo  
tFifo  
cnfgA  
cnfgB  
ecr  
010  
011  
110  
111  
111  
All  
Parallel Port Data FIFO  
ECP FIFO (DATA)  
Test FIFO  
Configuration Register A  
Configuration Register B  
Extended Control Register  
+401h R/W  
+402h R/W  
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.  
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.  
Table 19 - Mode Descriptions  
MODE  
DESCRIPTION  
(Refer to ECR Register Description)  
000  
001  
010  
011  
100  
101  
110  
111  
SPP mode  
PS/2 Parallel Port mode  
Parallel Port Data FIFO mode  
ECP Parallel Port mode  
EPP mode (If this option is enabled in the configuration registers)  
(Reserved)  
Test mode  
Configuration mode  
5.4.4.1  
DATA and ecpAFifo PORT  
ADDRESS OFFSET = 00H  
Modes 000 and 001 (Data Port)  
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by  
RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the  
nIOW input. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.  
During a READ operation, PD0 - PD7 ports are read and output to the host CPU.  
Mode 011 (ECP FIFO - Address/RLE)  
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the  
ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the  
forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing  
Diagrams section of this data sheet .  
5.4.4.2  
DEVICE STATUS REGISTER (dsr)  
ADDRESS OFFSET = 01H  
SMSC DS – SP37E760  
Rev. 04/13/2001  
 复制成功!