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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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5.4 EXTENDED CAPABILITIES PARALLEL PORT  
ECP provides a number of advantages, some of which are listed below. The individual features are explained in  
greater detail in the remainder of this section.  
High performance half-duplex forward and reverse channel  
Interlocked handshake, for fast reliable transfer  
Optional single byte RLE compression for improved throughput (64:1)  
Channel addressing for low-cost peripherals  
Maintains link and data layer separation  
Permits the use of active output drivers  
Permits the use of adaptive signal timing  
Peer-to-peer capability  
5.4.1 VOCABULARY  
The following terms are used in this document:  
assert  
When  
state.  
a
signal asserts it transitions to a “true” state, when a signal deasserts it transitions to a “false”  
forward Host to Peripheral communication.  
reverse Peripheral to Host communication.  
Pword A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8  
bits.  
1
0
A high level  
A low level  
These terms may be considered synonymous:  
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PeriphClk, nAck  
HostAck, nAutoFd  
PeriphAck, Busy  
nPeriphRequest, nFault  
nReverseRequest, nInit  
nAckReverse, PError  
Xflag, Select  
ECPMode, nSelectln  
HostClk, nStrobe  
Reference Document:  
IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is  
available from Microsoft. The bit map of the Extended Parallel Port registers is shown in Table 16.  
Table 16 - ECP Registers  
D7  
PD7  
D6  
PD6  
D5  
D4  
D3  
PD3  
D2  
PD2  
D1  
PD1  
D0  
PD0  
data  
PD5  
PD4  
ecpAFifo2  
dsr1  
Addr/RLE  
nBusy  
0
Address or RLE field  
nAck  
0
PError  
Direction  
Select  
nFault  
0
nInit  
0
0
dcr1  
ackIntEn  
SelectIn  
autofd strob  
e
cFifo2  
ecpDFifo2  
tFifo2  
Parallel Port Data FIFO  
ECP Data FIFO  
Test FIFO  
cnfgA  
cnfgB  
ecr  
0
0
0
0
1
0
0
0
0
0
0
0
full  
0
0
compress  
intrValue  
MODE  
nErrIntrEn  
dmaEn  
serviceIntr  
empt  
y
Note1 These registers are available in all modes.  
Note2 All FIFOs use one common 16 byte FIFO.  
SMSC DS – SP37E760  
Rev. 04/13/2001  
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