Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 6.29 - Interrupt Control Table
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
PRIORIT
Y LEVEL
INTERRUPT
TYPE
INTERRUPT
SOURCE
RESET
BIT 3
0
BIT 2 BIT 1 BIT 0
CONTROL
0
0
1
-
None
None
-
Overrun Error,
Receiver Line
Status
Parity Error,
Reading the Line
Status Register
0
1
1
0
Highest
Framing Error or
Break Interrupt
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Received Data
Available
Receiver Data
Available
0
1
1
0
0
0
0
Second
Second
No Characters
Have Been
Removed From or
Input to the
Character
Timeout
Reading the
Receiver Buffer
Register
RCVR FIFO
1
during the last 4
Char times and
there is at least 1
char in it during
this time
Indication
Reading the IIR
Register (if
Transmitter
Holding
Transmitter
Holding Register
Empty
Source of
0
0
0
0
1
0
0
0
Third
Interrupt) or
Writing the
Register
Empty
Transmitter
Holding Register
Clear to Send or
Data Set Ready
or Ring Indicator
or Data Carrier
Detect
Reading the
MODEM Status
Register
MODEM
Status
Fourth
6.28.7 LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
Serial Data
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
82
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
