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LPC47M182-NR 参数 Datasheet PDF下载

LPC47M182-NR图片预览
型号: LPC47M182-NR
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O控制器,主板胶合逻辑 [ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC]
分类和应用: 控制器
文件页数/大小: 223 页 / 1215 K
品牌: SMSC [ SMSC CORPORATION ]
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Advanced I/O Controller with Motherboard GLUE Logic  
Datasheet  
These two bits specify the number of bits in each transmitted or received serial character. The encoding of  
bits 0 and 1 is as follows:  
The Start, Stop and Parity bits are not included in the word length.  
BIT 1  
BIT 0  
WORD LENGTH  
5 Bits  
0
0
1
1
0
1
0
1
6 Bits  
7 Bits  
8 Bits  
Bit 2  
This bit specifies the number of stop bits in each transmitted or received serial character. The following  
table summarizes the information.  
NUMBER OF  
STOP BITS  
BIT 2 WORD LENGTH  
0
1
1
1
1
--  
1
1.5  
2
2
2
5 bits  
6 bits  
7 bits  
8 bits  
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.  
Bit 3  
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive  
data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to  
generate an even or odd number of 1s when the data word bits and the parity bit are summed).  
Bit 4  
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is  
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic  
“1” an even number of bits is transmitted and checked.  
Bit 5  
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or  
Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space  
Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark  
Parity). If bit 5 is 0 Stick Parity is disabled.  
Bit 6  
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or  
logic “0” state and remains there (until reset by a low level bit 6) regardless of other transmitter activity.  
This feature enables the Serial Port to alert a terminal in a communications system.  
SMSC LPC47M182  
83  
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)  
DATASHEET  
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