Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Model 30 Mode
7
6
0
5
0
4
0
3
2
1
0
DSK CHG
DMAEN NOPREC DRATE DRATE
SEL1
1
SEL0
0
RESET
COND.
N/A
0
0
0
0
0
BITS 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 – 6 UNDEFINED
Always read as a logic “0”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register. This register is located in the Power Control
Logical Device (when LD_NUM=0) or Runtime Register Block Logical Device (when LD_NUM=1)at offset
0x18.
6.4.11 CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
7
0
6
0
5
0
4
0
3
0
2
0
1
0
DRATE DRATE
SEL1
1
SEL0
0
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 – 7 RESERVED
Should be set to a logical “0”
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
50
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
