Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev
1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
D7
PD7
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
data
ecpAFifo Addr/RLE
Address or RLE field
Select nFault
2
1
1
dsr
dcr
nBusy
0
nAck
0
PError
0
nInit
0
0
Direction ackIntEn SelectI
autofd strobe
n
cFifo
ecpDFifo
tFifo
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
2
2
2
cnfgA
cnfgB
ecr
0
0
0
1
0
0
0
0
compress intrValue
MODE
Parallel Port IRQ
Parallel Port DMA
nErrIntrE dmaEn serviceIntr
full
empty
n
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
Registers.
7.11 ECP Implementation Standard
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
7.11.1 Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of
gates to implement. It does not do any “protocol” negotiation, rather it provides an automatic high
burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the
maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic
handshake for the standard parallel port to improve compatibility mode transfer speed.
SMSC LPC47M182
103
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
