6.4 USB HUB FUNCTIONAL DESCRIPTION
The USB Hub Block implements one upstream port and up to four downstream ports. The internal
address/data/control connection is provided for programming by BIOS the USB Vendor ID, Product ID, Device
Revision Number and number of down stream ports by accessing the Hub Control register. USB cable data is not
transmitted or received via the internal connection.
The USB Hub Block implements the requirements defined in the USB Hub Device Class Specification Version 1.1
(USB Specification 1.1, Chapter 11), including Status Change Endpoint, Hub class specific descriptors and Hub class
specific requests. The USB Hub Block supports Suspend and Resume both as a USB device and in terms of
propagating Suspend and Resume signaling. It also supports remote wakeup by a device on downstream ports.
For wakeup requirements, the Hub Block is powered from VTR. VTR also powers the 24MHz OSC/PLL, 32 KHz clock
input buffer, 48MHz CLK/OSC MUX and all Logical Device and Global Configuration Registers as well as
programmable wakeup events in the PME interface.
The Hub Block clock requirements are derived from separate CLK/OSC pins (ICLK, OCLK). Clock pins ICLK and
OCLK provide implementation flexibility for the system designer (see FIGURE 2). When a 48MHz clock signal is
available, it may be connected directly to the ICLK pin. To reduce overall system EMI, a local 24MHz oscillator may
alternately be connected between the ICLK and OCLK pins. The OSC_CLK control bit in the Logical Device C
Configuration Register at 0xF0, selects between clock sources. The 32 KHz clock source is used to time certain port
change events. This will ensure the USB Hub will respond to port change events while the hub is in Suspend.
Clocks for IO
Blocks
To Hub Block
and SIO
48 Mhz. (to
Hub Block)
OSC_CLK
(from config.
registers)
CLK/OSC
MUX
PLL_EN
(control
PLL
Buffer
OSC/PLL
from hub)
OCLK
ICLK
CLOCKI
CLKI32
14.318 MHz. 32.768 KHz.
24 MHz.
Crystal
Clock
Clock
48 MHz.
Clock
FIGURE 2 – LPC47M14X CLOCK GENERATOR
For power conservation the USB Hub Block turns off internal hub clocks during Suspend, as follows:
ꢀ
The Hub Block responds to two types of Suspend. Selective (or Port) Suspend and Global Suspend.
Segments of the bus can be selectively suspended by sending the command SetPortFeature
(PORT_SUSPEND) to the hub port to which that segment is attached. The suspended port will block activity
to the suspended bus segment. Because other ports on the hub remain active, internal clocks are not turned
off.
ꢀ
Global Suspend is used when no communication is desired anywhere on the bus and the entire bus is
placed in the Suspend state. The host signals the start of global suspend by ceasing all its transmissions
(including the SOF token). As the hub block, and each device on the bus, recognizes that the bus is in the
idle state for the appropriate length of time, it goes into the Suspend state. Because all bus segments
attached to the hub are in the Suspend state, the hub will turn off the internal 24MHz driven PLL. In addition,
48MHz is stopped in the Hub Block. The 48MHz clock signal at the ICLK pin, if enabled, is not stopped.
Control logic external to the LPC47M14X should stop this clock, if desired.
ꢀ
The Hub Block will Resume from a Suspend state by receiving any non-idle signaling by a remote wakeup
enabled device on its downstream ports or Resume signaling on its upstream port. If the Hub has been
enabled as a remote wakeup source, it will also Resume from connects and disconnects on downstream
SMSC DS – LPC47M14X
Page 24
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
