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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
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Parallel Port  
Direct power management is controlled by CR22. Refer to CR22 for more information.  
Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks  
to be placed into powerdown when not being used.  
The EPP logic is in powerdown under any of the following conditions:  
1. EPP is not enabled in the configuration registers.  
2. EPP is not selected through ecr while in ECP mode.  
The ECP logic is in powerdown under any of the following conditions:  
1. ECP is not enabled in the configuration registers.  
2
SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.  
Exit Auto Powerdown  
The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when  
the parallel port mode is changed through the configuration registers.  
SERIAL IRQ  
The LPC47M10x supports the serial interrupt to transmit interrupt information to the host system. The serial  
interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.  
Timing Diagrams for SER_IRQ Cycle  
A) Start Frame timing with source sampled a low pulse on IRQ1  
START FRAME  
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME  
SL  
or  
H
R
T
S
R
T
S
R
T
S
R
T
H
PCI_CLK  
1
START  
SER_IRQ  
Drive Source  
IRQ1  
Host Controller  
None  
IRQ1  
None  
Note:  
H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample  
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge  
hierarchy in a synchronous bridge design.  
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.  
IRQ14  
FRAME  
R
IRQ15  
FRAME  
R
IOCHCK#  
FRAME  
STOP FRAME  
NEXT CYCLE  
START  
2
S
T
S
T
S
R
T
H
R
T
I
PCI_CLK  
SER_IRQ  
Driver  
1
3
STOP  
None  
IRQ15  
None  
Host Controller  
Note:  
H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle  
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-  
around clock of the Stop Frame.  
Note 2: There may be none, one or more Idle states during the Stop Frame.  
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.  
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