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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 72 - KYBD, Logical Device 7 [Logical Device Number = 0x07]  
NAME  
KRST_GA20  
REG INDEX  
DEFINITION  
KRESET and GateA20 Select  
STATE  
0xF0  
R/W  
Bit[7] Polarity Select for P12  
Default = 0x00  
on VCC POR,  
VTR POR and  
HARD RESET  
= 0 P12 active low (default)  
= 1 P12 active high  
Bit[6] M_ISO. Enables/disables isolation of mouse  
signals into 8042. Does not affect MDAT signal to mouse  
wakeup (PME) logic.  
1=block mouse clock and data signals into 8042  
0= do not block mouse clock and data signals into 8042  
Bit[5] K_ISO. Enables/disables isolation of keyboard  
signals into 8042. Does not affect KDAT signal to  
keyboard wakeup (PME) logic.  
1=block keyboard clock and data signals into 8042  
0= do not block keyboard clock and data signals into  
8042  
Bit[4] MLATCH  
= 0 MINT is the 8042 MINT ANDed with Latched MINT  
(default)  
= 1 MINT is the latched 8042 MINT  
Bit[3] KLATCH  
= 0 KINT is the 8042 KINT ANDed with Latched KINT  
(default)  
= 1 KINT is the latched 8042 KINT  
Bit[2] Port 92 Select  
= 0 Port 92 Disabled  
= 1 Port 92 Enabled  
Bit[1] Reserved  
Bit[0] Reserved  
0xF1 - 0xFF  
Reserved - read as ‘0’  
Table 73 - PME, Logical Device A  
DEFINITION  
Bit[0] (CLK32_PRSN)  
NAME  
CLOCKI32  
REG INDEX  
0xF0  
STATE  
C
0=32kHz clock is connected to the CLKI32  
pin (default)  
1=32kHz clock is not connected to the CLKI32  
(R/W)  
Default = 0x00  
on VTR POR  
pin (pin is grounded)  
Bit[1] SPEKEY_EN. This bit is used to turn the logic  
for the “wake on specific key” feature on and off. It will  
disable the 32kHz clock input to the logic when turned  
off. The logic will draw no power when disabled.  
0= “Wake on specific key” logic is  
on (default)  
1= “Wake on specific key” logic is off  
Bits[7:2] are reserved  
Table 74 – MPU-401 [Logical Device Number = 0x0B]  
NAME  
MPU-401 Primary  
Base I/O Address  
High Byte  
REG INDEX  
0x60 R/W Bit[0] A8  
Bit[1] A9  
DEFINITION  
STATE  
C
Bit[2] A10  
Bit[3] A11  
Default = 0x03  
Bit[4] “0”  
on HARD RESET,  
SOFT RESET, VCC  
POR and VTR POR  
MPU-401 Primary  
Bit[5] “0”  
Bit[6] “0”  
Bit[7] “0”  
0x61 R/W Bit[0] “0”  
C
Page 158  
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