欢迎访问ic37.com |
会员登录 免费注册
发布采购

LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47M10X_07的Datasheet PDF文件第152页浏览型号LPC47M10X_07的Datasheet PDF文件第153页浏览型号LPC47M10X_07的Datasheet PDF文件第154页浏览型号LPC47M10X_07的Datasheet PDF文件第155页浏览型号LPC47M10X_07的Datasheet PDF文件第157页浏览型号LPC47M10X_07的Datasheet PDF文件第158页浏览型号LPC47M10X_07的Datasheet PDF文件第159页浏览型号LPC47M10X_07的Datasheet PDF文件第160页  
Table 70 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]  
NAME  
Serial Port 1  
REG INDEX  
0xF0 R/W Bit[0] MIDI Mode  
DEFINITION  
STATE  
C
Mode Register  
= 0  
= 1  
MIDI support disabled (default)  
MIDI support enabled  
Default = 0x00  
on VCC POR,  
VTR POR and  
HARD RESET  
Bit[1] High Speed  
= 0  
= 1  
High Speed Disabled(default)  
High Speed Enabled  
Bit[6:2] Reserved, set to zero  
Bit[7]: Share IRQ  
=0 UARTS use different IRQs  
=1 UARTS share a common IRQ  
See Note 1 below.  
Note 1: To properly share and IRQ,  
1. Configure UART1 (or UART2) to use the desired IRQ.  
2. Configure UART2 (or UART1) to use No IRQ selected.  
3. Set the share IRQ bit.  
Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set,  
UART IRQs will assert when either UART generates an interrupt.  
then both of the  
UART Interrupt Operation  
Table 71 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]  
NAME  
REG INDEX  
DEFINITION  
STATE  
Serial Port 2  
0xF0 R/W Bit[0] MIDI Mode  
C
Mode Register  
= 0  
= 1  
MIDI support disabled (default)  
MIDI support enabled  
Default = 0x00  
on VCC POR,  
VTR POR and  
HARD RESET  
Bit[1] High Speed  
= 0  
= 1  
High Speed disabled(default)  
High Speed enabled  
Bit[4:2] Reserved, set to zero  
Bit[5] TXD2_MODE (Note 1)  
=0  
=1  
The inactive state of the TXD2 pin is low  
The state of the TXD2 pin is tristate  
Bits[7:6] Reserved. Set to zero.  
Page 156  
 复制成功!