TABLE 4 – REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
REGISTER
REGISTER
SYMBOL
ADDRESS
REGISTER NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(Note 1)
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
Receive Buffer Register (Read Only)
RBR
THR
IER
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(Note 2)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
Data Bit 7
0
Data Bit 6
0
Data Bit 5
0
Data Bit 4
0
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Enable
MODEM
Status
Enable
Receiver
Line
Enable
Transmitter
Holding
Enable
Received
Data
Interrupt
(EMSI)
Status
Register
Empty
Available
Interrupt
(ERDAI)
Interrupt
(ELSI)
Interrupt
(ETHREI)
ADDR = 2
ADDR = 2
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
IIR
FIFOs
Enabled
(Note 6)
RCVR
Trigger
MSB
FIFOs
Enabled
(Note 6)
0
0
Interrupt ID
Bit (Note 6)
Interrupt
ID Bit
Interrupt ID
Bit
“0” if
Interrupt
Pending
FIFO Enable
FCR
(Note 8)
RCVR
Reserved
Reserved
DMA Mode XMIT FIFO
RCVR
Trigger LSB
Select
Reset
FIFO Reset
(Note 7)
ADDR = 3
Line Control Register
LCR
Divisor
Latch
Set Break
0
Stick Parity Even Parity
Parity
Enable
(PEN)
Number of
Stop Bits
(STB)
Word
Length
Word Length
Select Bit 0
(WLS0)
Select
(EPS)
Access Bit
(DLAB)
Select Bit 1
(WLS1)
ADDR = 4
ADDR = 5
MODEM Control Register
Line Status Register
MCR
LSR
0
0
Loop
OUT2
(Note 4)
OUT1
(Note 4)
Request to
Send (RTS)
Data
Terminal
Ready (DTR)
Error in
RCVR FIFO
(Note 6)
Transmitter Transmitter
Break
Interrupt
(BI)
Framing
Parity
Overrun
Data Ready
Empty
Holding
Register
(THRE)
Error (FE)
Error (PE) Error (OE)
(DR)
(TEMT)
(Note 3)
ADDR = 6
MODEM Status Register
MSR
Data
Ring
Indicator
(RI)
Data Set
Ready
Clear to
Delta Data
Carrier
Trailing
Delta Data
Delta Clear
to Send
Carrier
Detect
(DCD)
Send (CTS)
Edge Ring Set Ready
(DSR)
Detect
Indicator
(DDSR)
(DCTS)
(DDCD)
(TERI)
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Scratch Register (Note 5)
Divisor Latch (LS)
SCR
DDL
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Divisor Latch (MS)
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SMSC LPC47B27x
- 66 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
