Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
4.2.3.1
4.2.3.2
4.2.3.3
Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the PHY2_RST bit of the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x).
Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared.
No other modules of the LAN9313/LAN9313i are affected by this reset.
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to Section 7.2.9, "PHY Power-Down Modes," on page 96 for additional
information.
Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the Reset Control
Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY2_RST and Reset bit will
clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 2 PHY, register bits designated as NASR are not
reset.
Refer to Section 7.2.10, "PHY Resets," on page 97 for additional information on Port 2 PHY resets.
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the PHY1_RST bit of the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x).
Upon completion of the Port 1 PHY reset, the PHY1_RST and Reset bits are automatically cleared.
No other modules of the LAN9313/LAN9313i are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to Section 7.2.9, "PHY Power-Down Modes," on page 96 for additional
information.
Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the Reset Control
Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY1_RST and Reset bit will
clear approximately 110uS after the Port 1 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not
reset.
Refer to Section 7.2.10, "PHY Resets," on page 97 for additional information on Port 1 PHY resets.
Virtual PHY Reset
A Virtual PHY reset is performed by setting the VPHY_RST bit of the Reset Control Register
(RESET_CTL) or Reset in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL). No other
modules of the LAN9313/LAN9313i are affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the Reset Control
Register (RESET_CTL) or the Reset bit in the Virtual PHY Basic Control Register
(VPHY_BASIC_CTRL) until it clears. Under normal conditions, the VPHY_RST and Reset bit will clear
approximately 1uS after the Virtual PHY reset occurrence.
Refer to Section 7.3.3, "Virtual PHY Resets," on page 100 for additional information on Virtual PHY
resets.
Revision 1.2 (04-08-08)
SMSC LAN9313/LAN9313i
DATA4S4HEET
SMSC [ SMSC CORPORATION ]
