Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.1.2
GPIO/LED
This section details the General Purpose I/O (GPIO) and LED related System CSR’s.
13.1.2.1
General Purpose I/O Configuration Register (GPIO_CFG)
Offset:
1E0h
Size:
32 bits
This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins
is configured here as well as the IEEE 1588 timestamping and clock compare event output properties
of the GPIO[9:8] pins.
BITS
DESCRIPTION
TYPE
DEFAULT
31:30
29:28
RESERVED
RO
-
GPIO 1588 Timer Interrupt Clear Enable 9-8
(GPIO_1588_TIMER_INT_CLEAR_EN[9:8])
R/W
00b
These bits enable inputs on GPIO9 and GPIO8 to clear the
1588_TIMER_INT bit of the 1588 Interrupt Status and Enable Register
(1588_INT_STS_EN). The polarity of these inputs is determined by
GPIO_INT_POL[9:8].
Note:
The GPIO must be configured as an input for this function to
operate. For the clear function, GPIO inputs are edge sensitive and
must be active for greater than 40 nS to be recognized.
27:16
GPIO Interrupt Polarity 11-0 (GPIO_INT_POL[11:0])
R/W
0h
These bits set the interrupt polarity of the 12 GPIO pins. The configured
level (high/low) will set the corresponding GPIO_INT bit in the General
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN).
0: Sets low logic level trigger on corresponding GPIO pin
1: Sets high logic level trigger on corresponding GPIO pin
GPIO_INT_POL[9:8] also determines the polarity of the GPIO IEEE 1588
time clock capture events and the GPIO 1588 Timer Interrupt Clear inputs.
Refer to Section 12.2, "GPIO Operation," on page 142 for additional
information.
15:14
1588 GPIO Output Enable 9-8 (1588_GPIO_OE[9:8])
These bits configure GPIO 9 and GPIO 8 to output 1588 clock compare
events.
R/W
0h
0: Disables the output of 1588 clock compare events
1: Enables the output of 1588 clock compare events
Note:
These bits override the direction bits in the General Purpose I/O
Data & Direction Register (GPIO_DATA_DIR) register. However,
the GPIO buffer type (GPIOBUF[11:0]) in the General Purpose I/O
Configuration Register (GPIO_CFG) is not overridden.
13
12
GPIO 9 Clock Event Polarity (GPIO_EVENT_POL_9)
This bit determines if the 1588 clock event output on GPIO 9 is active high
or low.
R/W
R/W
1b
1b
0: 1588 clock event output active low
1: 1588 clock event output active high
GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8)
This bit determines if the 1588 clock event output on GPIO 8 is active high
or low.
0: 1588 clock event output active low
1: 1588 clock event output active high
SMSC LAN9313/LAN9313i
155
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
