Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.1.1.2
Interrupt Status Register (INT_STS)
Offset:
058h
Size:
32 bits
This register contains the current status of the generated interrupts. A value of 1 indicates the
corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions
have not been met. The bits of this register reflect the status of the interrupt source regardless of
whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where
indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
BITS
DESCRIPTION
Software Interrupt (SW_INT)
This interrupt is generated when the SW_INT_EN bit of the Interrupt Enable
Register (INT_EN) is set high. Writing a one clears this interrupt.
TYPE
DEFAULT
31
R/WC
0b
30
29
Device Ready (READY)
R/WC
RO
0b
0b
This interrupt indicates that the LAN9313/LAN9313i is ready to be
accessed after a power-up or reset condition.
1588 Interrupt Event (1588_EVNT)
This bit indicates an interrupt event from the IEEE 1588 module. This bit
should be used in conjunction with the 1588 Interrupt Status and Enable
Register (1588_INT_STS_EN) to determine the source of the interrupt
event within the 1588 module.
28
Switch Fabric Interrupt Event (SWITCH_INT)
RO
0b
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the Switch Global Interrupt Pending Register
(SW_IPR) to determine the source of the interrupt event within the Switch
Fabric.
27
26
Port 2 PHY Interrupt Event (PHY_INT2)
RO
RO
0b
0b
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x).
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the Port x PHY Interrupt Source
Flags Register (PHY_INTERRUPT_SOURCE_x).
25:20
19
RESERVED
RO
-
GP Timer (GPT_INT)
This interrupt is issued when the General Purpose Timer Count Register
(GPT_CNT) wraps past zero to FFFFh.
R/WC
0b
18:13
12
RESERVED
RO
RO
-
GPIO Interrupt Event (GPIO)
0b
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the General Purpose
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
11:0
RESERVED
RO
-
SMSC LAN9313/LAN9313i
153
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
