Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
13.1.1.3
Interrupt Enable Register (INT_EN)
Offset:
05Ch
Size:
32 bits
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables
the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register (with the exception of SW_INT_EN). For descriptions of each interrupt, refer
to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register.
BITS
DESCRIPTION
TYPE
DEFAULT
31
30
Software Interrupt Enable (SW_INT_EN)
Device Ready Enable (READY_EN)
1588 Interrupt Event Enable (1588_EVNT_EN)
Switch Engine Interrupt Event Enable (SWITCH_INT_EN)
Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)
Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
RO
0b
0b
0b
0b
0b
0b
-
29
28
27
26
25:20
19
GP Timer Interrupt Enable (GPT_INT_EN)
RESERVED
R/W
RO
0b
-
18:13
12
GPIO Interrupt Event Enable (GPIO_EN)
RESERVED
R/W
RO
0b
-
11:0
Revision 1.2 (04-08-08)
154
SMSC LAN9313/LAN9313i
DATASHEET
SMSC [ SMSC CORPORATION ]
