High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 8 DWORD read cycles, or 16 WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Figure 6.2 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.4 PIO Burst Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcsh
tcsdv
tacyc
tasu
tadv
tah
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
13
ns
ns
30
45
0
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
ns
40
7
0
0
ns
ns
ns
ns
tdon
tdoff
tdoh
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
0
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
SMSC LAN9218
117
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
